Serdes Analog Architect, US, CH, UK, DE
Vue: 226
Jour de mise à jour: 26-03-2024
Localisation: Lausanne Vaud VD
Catégorie: Conception - Web Arts / Design Architecture / Design dintérieur IT - Logiciel
Industrie: Electrical Electronic Manufacturing Computer Hardware Semiconductors
Niveau: Associate
Type d’emploi: Full-time
le contenu du travail
At Kandou, we are a team of passionate professionals striving to make a mark in the trajectory of the semiconductor industry. If you love to be part of a start-up that is challenging established tech giants and you are a proactive problem-solver, able to multitask in a high energy environment and someone who is motivated by pushing their limits and challenging the status quo, we have just the opportunity for you.We are actively seeking a resourceful Serdes Analog Architect either based in US, Lausanne (CH), Northampton/Reading (UK) or Dortmund (DE)
Key responsibilities
- Write and own content of analog specifications at chip, block and interface level.
- Specify block level requirements (jitter budget, power budget, etc.) to achieve system requirements at the chip level.
- Working closely with analog, digital and verification teams to ensure design meets analog architecture specifications including review and sign-off authority regarding deviations from specification.
- Participate in standards bodies and represent company interests in those bodies.
- Responsibility for analog design and debug of assigned analog blocks (when appropriate).
- Work on cross-functional teams to implement improvement actions to optimise design cost, quality and /or schedule as appropriate.
- Bachelor of Engineering in Electronics and Electrical Engineering (equivalent or higher).
- 10+ years of experience in the semiconductor industry.
- 5+ years of experience in Serdes architecture and design.
- Proven experience with high speed Serdes analog design, system architectures, and ecosystems.
- Proven experience with decomposing and partitioning specifications between analog and digital domains, and within analog domains to optimize design architecture.
- Experience writing specifications at the chip and block levels and writing interface specifications for interfaces external and internal to the chip.
- Experience in leading and working with teams across different geographical sites.
- Experience with representing the design team and presenting to customers.
- Familiarity with Serdes architectures and associated analog circuits, including Receiver architectures, Transmitter architectures, and Phase-Locked Loop designs.
- Proficient at partitioning chip level requirements to specifications at the block level.
- Knowledge of digital and analog design flows.
- Proficient at analog design using Cadence tools.
- Proficient debug skills to identify bugs in analog architecture, functionality and performance.
- Demonstrated team building and leadership skills, including working with cross-functional teams.
- Must possess strong communication skills including the ability to write specifications and internal/external presentations.
Date limite: 10-05-2024
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