PhD position: Scalable Parallel Architectures for 5G/6G wireless systems

The Digital Circuits and Systems Group (Prof. L. Benini IIS-Digital) is a research group at the Dept. of Information Technology and Electrical Engineering at ETH Zurich. The group is looking for a talented and motivated individual with a MS in Electrical Engineering willing to pursue a PhD project on design and implementation of highly parallel and flexible open-source multicore architectures for efficient and scalable baseband processing in future 5G and 6G wireless systems.

We are looking for a talented and highly motivated candidate with an electrical engineering background (MS-EE or MS-EE, possibly with 1-2 years of industry experience) to join our group as a PhD student. The PhD research activities will focus on the design and implementation of open-source (RISC-V based) parallel hardware architecture for baseband processing in 5G and 6G wireless systems, with specific emphasis on scalable computational capabilities and high energy efficiency. The architecture be based on customizable open-source RISC-V cores, interconnects and support infrastructure developed at IIS-Digital (pulp-platform.org). Performance and efficiency improvements will leverage ISA specialization and application-specific coprocessors.

The main application scenario is the radio access network (RAN) disaggregation of the 5G and 6G protocol stack where softwarization and virtualization of the network components pose significant challenges to the underlying hardware architectures in terms of both computational capabilities and energy efficiency.

The preferred start is March 1st, 2022 but later start is possible.

Required

• Recently (less than 3 years) obtained Master degree in electrical engineering, computer engineering, or equivalent (Applicant cannot hold a PhD degree obtained previously).
• Strong experience in RTL design (working knowledge of SystemVerilog or Verilog).
• Experience with industrial frond-end EDA flows for VLSI design and implementation (Synopsys/Cadence/Mentor)
• Experience with C/C++ embedded programming
• Solid background on signal processing and wireless communications

Desirable

• Basic knowledge of advanced communication systems and standards (5G and beyond)
• Exposure to parallel programming and parallel computer architecture

Soft Skills

• Good communication and interpersonal skills
• Willingness to work in a diverse, internationally distributed team.
• Adaptability and flexibility towards the open-ended problems associated with a research environment.
• Self-motivation and capability of independent learning

We look forward to receiving your online application with the following documents:

• CV
• Motivation letter explaining why you are the best candidate

Please note that we exclusively accept applications submitted through our online application portal. Applications via email or postal services will not be considered. Questions regarding the position should be directed to Michele Magno (no applications).

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